1. Field of the Invention
The present invention relates to the area of data communication, and more particularly to method and system for multiple master devices to access slave devices via a data bus (e.g., a unibus).
2. Description of Related Art
In data communications, most bus architectures are that one master device connects to one or more slave devices, in which the master device has complete control power over the bus, a slave device occupies the bus only when required by the master device and carries out data communication with the master device. If there are many master devices in one system (for example, a computer with multiple CPUs) and one slave device has to communicate with one or more master devices, the operation can be logically confused if not properly implemented.
In order to alleviate the problem, a conventional system is shown in FIG. 1 in which the system includes four master devices 101-104, four slave devices 105-108. Each of the master devices 101-104 communicates with one of the slave device 105-108 through a respective bus (e.g., bus1, bus2, bus3, or bus4). Each of the master devices 101-104 and each of the slave devices 105-108 are corresponding to each other, and each bus is corresponding to a pair of master device and slave device. Thus it guarantees no conflict among the buses by adopting this configuration, but it occupies more buses which lead to the waste of system resources.
In order to reduce the waste caused by buses, another conventional system is shown in FIG. 2, which includes five master devices 201-205, one slave device 206. In other words, the master device 201 serves as an occupant of the bus. When one of the master devices 202-205 needs to use the bus, it has to send a request to the master device 201. When the master device 201 detects that the bus is idle, it immediately sends confirmation signals to the requesting master device that has asked for the bus, then the requesting master device can communicate with slave device 206 via the master device 201 over the bus. This configuration reduces the waste of the bus, but it needs to add one more master device to serve as a management device of the bus, and the master device includes at least one chip such as a processor which increases the costs of the entire system.
Thus there is a need for techniques for multiple master devices that may access one or more slave device via a single data bus.